Integrated circuits (ICs) and packages have become increasingly more complex as clock speeds have exceeded the gigahertz milestone. As a result, it has become increasingly important for IC designers to investigate the performance of designs prior to actual fabrication. A common mechanism to complete this investigation is to simulate input/outputs buffers (I/Os) with modeling to determine the high speed effects on signal integrity, power supply, collapse, noise, etc. Modeling may be completed, for example, using conventional modeling software such as SPICE available from a variety of electronic design automation (EDA) vendors.
One particular performance characteristic that is modeled is Simultaneous Switching Output (SSO) Noise (also referred to as simultaneous switching noise, ground bounce, etc.). The simultaneous switching of multiple I/O drivers on the same chip can cause a temporary voltage variation inside the chip. This temporary voltage variation is referred to as noise. Normally, a small amount of noise is deemed tolerable. However, larger amplitudes of noise may cause the chip to behave in an undesirable fashion. Accordingly, SSO noise of a chip design is often tested via modeling (e.g., simulation) to determine whether it falls within acceptable limits.
Conventional modeling software allows simulation of node switching of the circuits/signals and calculates results such as node voltage, waveform, etc. Ideally, a thorough investigation of design performance would be expected to simulate the entire IC and package. However, simulating an entire IC and package or even a large area thereof, is impracticable due to the large number of circuit elements used on the new ICs.
One common approach of analyzing SSO noise has been to reduce modeling area to a small region (e.g., area, window, etc.) of the chip and package because of the complexity of the structures and I/O models. This small region approach is sometimes referred to as the Generic Package Model (GPM) in an application-specific integrated circuit (ASIC). It gives a worst case result of the noise when modeling the highest density I/O region in the chip/package.
However, the conventional noise modeling technique described above ignores the effects of neighboring areas adjacent to the modeling area. Because of this, conventional noise modeling techniques do not provide an accurate analysis of the SSO noise that will be seen in a manufactured chip.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.